module bcd_3(clk50m,reset,HEX0,HEX1,HEX2);
	input clk50m,reset;
	output [0:6]HEX0,HEX1,HEX2;
	reg [25:0]cnt;
	reg [11:0]clk1;
	reg [3:0]addr2,addr1,addr0;
	/*分频模块*/
	always @(posedge clk50m or negedge reset)begin
		if(!reset) begin
			cnt<=0; end
		else if(cnt==26'd10000000) 
			begin cnt<=0;clk1<=~clk1;end
		else 
			cnt<=cnt+1;
	end

	/*计数模块*/
	always @(posedge clk1 or negedge reset) begin
		if(!reset) begin
			addr0<=4'd0;
			addr1<=4'd0;
			addr2<=4'd0;end
		else if(addr0==4'd9&&addr1==4'd9) begin
			addr0<=4'd0;
			addr1<=4'd0;
			addr2<=addr2+4'd1;end
		else if(addr0==4'd9&&addr1!=4'd9)begin
			addr0<=4'd0;
			addr1<=addr1+4'd1;end
		else
			addr0<=addr0+4'd1;
	end
	show_decode4_7 u1(addr0,HEX0);
	show_decode4_7 u2(addr1,HEX1);
	show_decode4_7 u3(addr2,HEX2);
endmodule

//显示模块
module show_decode4_7(ST,HEX);
	input [3:0]ST;
	output reg[0:6] HEX;
	always @(ST) begin
		case(ST)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;

			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			default: HEX=~7'b0000000;
		endcase
	end
endmodule

